The scaling of conventional complementary metal-oxide-semiconductor field effect transistor (CMOSFET) faces challenges of rapid increase in power consumption. Tunnel field effect transistor (TFET) is a promising candidate enabling further scaling of power supply voltage without increase of off-state leakage current due to its sub-60 mV/dec subthreshold swing. However, input/output (I/O) devices normally have thicker gate dielectric and larger device dimensions. The I/O TFET devices are difficult to be fabricated when integrated with TFET devices.
Accordingly, there is a need for a structure having TFET device and planar I/O devices integrated together and a method making the same to address these concerns.